Conventionally, peripheral circuits of a dynamic random access memory (DRAM) comprising one-transistor one-capacitor type memory cells are constituted by N-channel metal oxide semiconductor (MOS) transistors in most cases. However, due to the recent improvement in the integration density of the DRAM, there is a tendency to use complementary metal oxide semiconductor (CMOS) transistors in the peripheral circuits of the DRAM. One reason the CMOS transistors are used in the peripheral circuits of the DRAM is that the construction of the peripheral circuits becomes simple. In other words, when pre-charging a circuit which performs a dynamic operation, it is possible to pre-charge the circuit at a sufficiently high speed to a power source voltage by use of P-channel transistors constituting the CMOS transistors. Accordingly, unlike in the conventional case, it is unnecessary to use a clock signal having a level which is raised to a level over the power source voltage by means of a bootstrap circuit or the like.
As a result, the voltages used within the circuit are in the range of the power source voltage, and an abnormally high voltage will not be applied to the transistors. For this reason, it is possible to reduce the undesirable effects of hot electrons. In addition, th circuit construction is simple because it is unnecessary to provide the bootstrap circuit or the like.
Recently, sense amplifiers are also constituted by CMOS transistors because the peripheral circuits of the DRAM are constituted by the CMOS transistors in order to take advantage of the advantageous features described before. As a result, although a conventional active restore circuit occupies a large area due to the complex circuit construction thereof, it becomes possible to realize the active restore circuit by use of simple latch circuits in the form of flip-flops. It becomes possible to construct the active restore circuit by use of only two transistors. According to the sense amplifier constituted by the CMOS transistors, a pair of bit lines are pre-charged to a high level, and the potential at one of the bit lines always falls due to the sense operation of the sense amplifier.
As will be described later on in the present specification in conjunction with the drawings, first and second bit lines are initially pre-charged to a predetermined voltage. When the potential at a word line rises, cell voltages are obtained at the first and second bit lines. The potential of the first bit line falls at a first line t1 when the sense amplifier operates. At the same time, the potential at the second bit line also falls slightly. Then, when the active restore circuit operates at a second time t2, the potential at the first bit line rises slightly due to noise and thereafter falls, while the potential at the second bit line rises up to the power source voltage. However, the bit line and a cell plate of the memory cell are coupled via a parasitic capacity. Conventionally, the potential of the cell plate is set to the ground level in most cases and the potential of the cell plate is relatively stable. But a bias at one-half the power source voltage is recently employed so as to relieve the absolute value of the electrical field in the memory capacitor, and in such a case, the potential of the cell plate becomes quite unstable. The reason why the bias at one-half the power source voltage is employed is because the memory capacitor uses a silicon dioxide (SiO.sub.2) film having a film thickness in the order of 100 to 200 (.ANG.) as the dielectric film and a dielectric breakdown will occur when a high voltage is applied thereto.
Usually, the voltage of one-half the power source voltage is obtained by use of a pair of voltage dividing resistors having high resistances. The voltage dividing resistors have the high resistances in order to prevent an unnecessary current flow which causes unnecessary power consumption. Since the impedance of the cell plate is extremely high with respect to the power source, the potential of the cell plate fluctuates when the potential at the bit line falls, due to the capacitive coupling between the bit line and the cell plate.
Accordingly, when the potential at the bit line falls between the first and second times t1 and t2, the potential of the cell plate which is coupled to the bit line via the parasitic capacity fluctuates locally and instantaneously. This fluctuation in the potential of the cell plate generates the so-called bump noise and causes erroneous read-out of a datum from the memory cell. In other words, when the bump noise occurs, the read-out voltage decreases in correspondence with a difference between the potentials of the cell plate at the time of the write-in and at the time of the read-out. In extreme cases, the datum may be sensed as a datum opposite to the actual datum. In addition, in the case where the memory cell array is positioned in a well of a CMOS structure and the potential of the cell plate fluctuates as described above, the potential of the well which forms a capacitive coupling with the cell plate undergoes a transitional change. As a result, the P-N junction within the well may become partially forward biased and cause latchup.
On the other hand, when the potential at the bit line changes from a high level to a low level or vice versa, a large current flows to a power source voltage supplying line or a ground line, and this large current generates noise in the bit line. As a result, there is a problem in that the semiconductor memory device may perform an erroneous operation due to such noise in the bit line.